## page was renamed from Kernel/Reference/fwts/mpcheck
== Firmware Test Suite - mpcheck test ==

This test sanity checks any existing Multi Processor tables against the 
the [[http://download.intel.com/design/pentium/datashts/24201606.pdf|MultiProcessor Specification]]. The Multi``Processor Specification describes enhancements to both operating systems and firmware allowing them to work with x86 processors in a multi-processor system.

Typical output from the mpcheck test is as follows:

{{{
Check MultiProcessor Tables.
--------------------------------------------------------------------------------
Test 1 of 9: Check MP header.
PASSED: Test 1, MP header looks sane.

Test 2 of 9: Check MP CPU entries.
PASSED: Test 2, All 4 CPU entries look sane.

Test 3 of 9: Check MP Bus entries.
PASSED: Test 3, All 4 Bus Entries looked sane.

Test 4 of 9: Check MP IO APIC entries.
PASSED: Test 4, All 1 IO APIC Entries look sane.

Test 5 of 9: Check MP IO Interrupt entries.
PASSED: Test 5, All 65 IO Interrupt Entries look sane.

Test 6 of 9: Check MP Local Interrupt entries.
PASSED: Test 6, All 2 Local Interrupt Entries look sane.

Test 7 of 9: Check MP System Address entries.
PASSED: Test 7, All 3 System Address Space Mapping Entries looks sane.

Test 8 of 9: Check MP Bus Hierarchy entries.
PASSED: Test 8, All 1 Bus Hierarchy Entries look sane.

Test 9 of 9: Check MP Compatible Bus Address Space entries.
PASSED: Test 9, All 2 Compatible Bus Address Space Entries look sane.

================================================================================
9 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.
================================================================================
}}}

=== Example: ===

{{{
sudo fwts mpcheck - 
}}}

..runs the mpcheck test on your machine and dumps the output to stdout.

== Explanation of test results ==

Certain test results may require a little more explanation. This section will try and give some context to specific test failures.

||Error ID||Explanation||
||MP``CPU``Entry``LAPIC``Id||The first Local APIC ID was not zero.||
||MP``CPU``Entry``LAPIC``Id||The Local APIC ID of a CPU entry was not the expected value. Local APIC IDs should be enumerated sequentially according to the specification.||
||MP``CPU``Entry``LAPIC``Version||The Local APIC CPU entry did not have the expected version number.||
||MP``CPU``Entry``Boot``CPU||A CPU entry that isn't the first one has been flagged as the boot CPU. Only the first CPU should be the boot CPU.||
||MP``CPU``Entry``Usable||Not CPU entries were flagged as boot CPUs. There must be at least one boot CPU.||
||MP``Bus``Entry``Bus``Type||A Multi``Processor bus entry has an unrecognised bus type.||
||MP``Bus``Entry``LAPIC``Id||A bus entry has a non-zero local APIC ID and hence does not conform to the specification.||
||MP``Bus``Entry``Bus``Id||A bus entry has an invalid bus ID.||
||MP``IOAPIC``Null``Addr||An IO APIC entry has an invalid (NULL) address. It must be defined.||
||MP``IOAPIC``Id||An IO APIC entry as an invalid APIC ID.||
||MP``IOAPIC``Id``Series|| An IO APIC entry has an APIC ID that does not follow the previous IO APIC entry APIC ID.||
||MP``IOAPIC``Enabled||Non of the IO APIC entries were marked as enabled.||
||MP``IOIRQ``Type||An IO Interrupt entry does not have a type in the range 0x00..0x03.||
||MP``IOAPIC``Id||An IO Interrupt entry has a destination IO APIC ID which refers to an IO APIC that has not been defined.||
||MP``Local``IRQ``Type||A Local Interrupt entry does not have a type in the range 0x00..0x03.||
||MP``Local``IRQ``Dest``IRQ``APID``Id||A Local Interrupt entry has a destination IO APIC ID which refers to an IO APIC that has not been defined.||
||MP``Sys``Addr``Space``Bus``Id||A System Address Space Mapping entry has a bus ID that is not defined in any of the Bus Entries.||
||MP``Sys``Addr``Space``Type||A System Address Space Mapping entry has an incorrect address type. It should be in the range 0x00..0x03.||
||MP``Sys``Addr``Space``Addr``Length||A System Address Space Mapping entry has a zero sized Address Length.||
||MP``Bus``Hieraracy``Length||A Bus Hierarchy entry has an incorrect length.||
||MP``Bus``Hierarchy``Parents||A Bus Hierarchy entry did not have any parents that connected to a top level Bus entry.||
||MP``Compat``Bus``Length||A Compatible Bus Address Space entry had an invalid length.||
||MP``Compat``Bus``Range``List||A Compatible Bus Address Space entry had an invalid range list. The value should be 0x00 or 0x01.||
||MP``Header``Sig||The Multi``Processor table header signature was incorrect.||
||MP``Header``Revision||The Multi``Processor table header revision was not 0x01 or 0x04.||
||MP``Header``LAPIC``Addr``Null||The Multi``Processor table header Local APIC address was NULL.||