## page was renamed from Kernel/Reference/fwts/msr == Firmware Test Suite - msr test == Intel and AMD processors provide special control registers known as [[http://en.wikipedia.org/wiki/Model-specific_register|Model Specific Registers]] (MSRs) allowing software to set and define specific features. The msr test will sanity check a range of MSRs to ensure consistency across CPUs and ensure sane values are configured by the firmware. Five specific tests are performed: * Check CPU generic MSRs (ones common to most processors). * Check CPU specific model MSRs. * Check all P State Ratios. * Check C1 and C3 autodemotion. * Check SMRR MSR registers. Typical output from this test is as follows: {{{ MSR register tests. --------------------------------------------------------------------------------------------------- Test 1 of 5: Check CPU generic MSRs. PASSED: Test 1, MSR P5_MC_TYPE (0x1) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MONITOR_FILTER_SIZE (0x6) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR PLATFORM_ID (0x17) (mask:1c000000000000) was consistent across 4 CPUs. PASSED: Test 1, MSR EBL_CR_POWERON (0x2a) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR APIC_BASE (0x1b) (mask:fffffffffffffeff) was consistent across 4 CPUs. PASSED: Test 1, MSR FEATURE_CONTROL (0x3a) (mask:ff07) was consistent across 4 CPUs. PASSED: Test 1, MSR BIOS_SIGN_ID (0x8b) (mask:ffffffff00000000) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRRCAP (0xfe) (mask:fff) was consistent across 4 CPUs. PASSED: Test 1, MSR SYSENTER_CS (0x174) (mask:ffff) was consistent across 4 CPUs. PASSED: Test 1, MSR SYSENTER_ESP (0x175) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR SYSENTER_EIP (0x176) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MCG_CAP (0x179) (mask:1ff0fff) was consistent across 4 CPUs. PASSED: Test 1, MSR MCG_STATUS (0x17a) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR CLOCK_MODULATION (0x19a) (mask:1f) was consistent across 4 CPUs. PASSED: Test 1, MSR THERM_INTERRUPT (0x19b) (mask:180801f) was consistent across 4 CPUs. PASSED: Test 1, MSR MISC_ENABLE (0x1a0) (mask:400c51889) was consistent across 4 CPUs. PASSED: Test 1, MSR PACKAGE_THERM_INTERRUPT (0x1b2) (mask:1ffff17) was consistent across 4 CPUs. PASSED: Test 1, MSR SMRR_PHYSBASE (0x1f2) (mask:fffff0ff) was consistent across 4 CPUs. PASSED: Test 1, MSR SMRR_PHYSMASK (0x1f3) (mask:fffff800) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSBASE0 (0x200) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSMASK0 (0x201) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSBASE1 (0x202) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSMASK1 (0x203) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSBASE2 (0x204) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSMASK2 (0x205) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSBASE3 (0x206) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSMASK3 (0x207) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSBASE4 (0x208) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSMASK4 (0x209) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSBASE5 (0x20a) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSMASK5 (0x20b) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSBASE6 (0x20c) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSMASK6 (0x20d) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSBASE7 (0x20e) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSMASK7 (0x20f) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSBASE8 (0x210) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSMASK8 (0x211) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSBASE9 (0x212) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_PHYSMASK9 (0x213) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_FIX64K_000 (0x250) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_FIX16K_800 (0x258) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_FIX16K_a00 (0x259) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_FIX4K_C000 (0x268) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_FIX4K_C800 (0x269) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_FIX4K_D000 (0x26a) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_FIX4K_D800 (0x26b) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_FIX4K_E000 (0x26c) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_FIX4K_E800 (0x26d) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_FIX4K_F000 (0x26e) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_FIX4K_F800 (0x26f) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR PAT (0x277) (mask:707070707070703) was consistent across 4 CPUs. PASSED: Test 1, MSR MC0_CTL2 (0x280) (mask:40007fff) was consistent across 4 CPUs. PASSED: Test 1, MSR MC1_CTL2 (0x281) (mask:40007fff) was consistent across 4 CPUs. PASSED: Test 1, MSR MC2_CTL2 (0x282) (mask:40007fff) was consistent across 4 CPUs. PASSED: Test 1, MSR MC3_CTL2 (0x283) (mask:40007fff) was consistent across 4 CPUs. PASSED: Test 1, MSR MC4_CTL2 (0x284) (mask:40007fff) was consistent across 4 CPUs. PASSED: Test 1, MSR MC5_CTL2 (0x285) (mask:40007fff) was consistent across 4 CPUs. PASSED: Test 1, MSR MC6_CTL2 (0x286) (mask:40007fff) was consistent across 4 CPUs. PASSED: Test 1, MSR MTRR_DEF_TYPE (0x2ff) (mask:c0f) was consistent across 4 CPUs. PASSED: Test 1, MSR PEBS_ENABLE (0x3f1) (mask:1) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_BASIC (0x480) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_PINPASED_CTLS (0x481) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_PROCBASED_CTLS (0x482) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_EXIT_CTLS (0x483) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_ENTRY_CTLS (0x484) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_MISC (0x485) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_CR0_FIXED0 (0x486) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_CR0_FIXED1 (0x487) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_CR4_FIXED0 (0x488) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_CR4_FIXED1 (0x489) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_VMX_VMCS_ENUM (0x48a) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_PROCBASED_CTLS2 (0x48b) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_EPT_VPID_CAP (0x48c) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_TRUE_PINBASED_CTLS (0x48d) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_TRUE_PROCBASED_CTLS (0x48e) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_TRUE_EXIT_CTLS (0x48f) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR VMX_TRUE_ENTRY_CTLS (0x490) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR EFER (0xc0000080) (mask:d01) was consistent across 4 CPUs. PASSED: Test 1, MSR STAR (0xc0000081) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR LSTAR (0xc0000082) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR FMASK (0xc0000084) (mask:ffffffffffffffff) was consistent across 4 CPUs. PASSED: Test 1, MSR KERNEL_GS_BASE (0xc0000102) (mask:ffffffffffffffff) was consistent across 4 CPUs. Test 2 of 5: Check CPU specific model MSRs. No model specific tests for model 0x3a. Test 3 of 5: Check all P State Ratios. PASSED: Test 3, MSR Minimum P-State (0xce) (mask:ff) was consistent across 4 CPUs. PASSED: Test 3, MSR Maximum P-State (0xce) (mask:ff) was consistent across 4 CPUs. Test 4 of 5: Check C1 and C3 autodemotion. PASSED: Test 4, MSR C1 and C3 Autodemotion (0xe2) (mask:3) was consistent across 4 CPUs. C1 and C3 Autodemotion enabled. Test 5 of 5: Check SMRR MSR registers. PASSED: Test 5, MSR SMRR_PHYSBASE (0x1f2) (mask:fffff) was consistent across 4 CPUs. PASSED: Test 5, MSR SMRR_TYPE (0x1f2) (mask:7) was consistent across 4 CPUs. PASSED: Test 5, MSR SMRR_PHYSMASK (0x1f3) (mask:fffff) was consistent across 4 CPUs. PASSED: Test 5, MSR SMRR_VALID (0x1f3) (mask:1) was consistent across 4 CPUs. =================================================================================================== 89 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only. =================================================================================================== }}} Note that the "mask:0x" shows the particular bits that were examined on each MSR. === Examples: === {{{ sudo fwts msr - }}} ..runs the msr test on your machine and dumps the output to stdout. {{{ sudo fwts msr }}} ..runs the msr test on your machine and appends the output to the default logfile results.log == Explanation of test results == Certain test results may require a little more explanation. This section will try and give some context to specific test failures. ||Error ID||Explanation|| ||MSR``CPUs``Inconsistent||A specific MSR is not consistently set across all CPUs.|| ||MSR``SMRR_PHYSBASE8MB``Boundary||SMRR_PHYSBASE is NOT on an 8MB boundary.|| ||MSR``SMRR_TYPE||SMRR_TYPE was expected to be 0x06 (Write-back).|| ||MSRSMRR``Region||SMRR region needs to be at least 8MB in size.|| ||MSRSMRRValidBit||SMRR valid bit is zero and should be one.||