msr

Differences between revisions 1 and 2
⇤ ← Revision 1 as of 2011-08-23 14:09:36 →
Size: 10653
Editor: colin-king
Comment:
← Revision 2 as of 2013-02-25 13:04:46 → ⇥
Size: 10625
Editor: cpc3-craw6-2-0-cust180
Comment:
Deletions are marked like this. Additions are marked like this.
Line 16: Line 16:
00013 msr MSR register tests.
00014 msr --------------------------------------------------------------------
00015 msr Test 1 of 5: Check CPU generic MSRs.
00016 msr PASSED: Test 1, MSR P5_MC_TYPE (0x1) (mask:ffffffffffffffff) was
00017 msr consistent across 2 CPUs.
00018 msr PASSED: Test 1, MSR MONITOR_FILTER_SIZE (0x6) (mask:ffffffffffffffff)
00019 msr was consistent across 2 CPUs.
00020 msr PASSED: Test 1, MSR PLATFORM_ID (0x17) (mask:1c000000000000) was
00021 msr consistent across 2 CPUs.
00022 msr PASSED: Test 1, MSR EBL_CR_POWERON (0x2a) (mask:ffffffffffffffff) was
00023 msr consistent across 2 CPUs.
00024 msr PASSED: Test 1, MSR APIC_BASE (0x1b) (mask:fffffffffffffeff) was
00025 msr consistent across 2 CPUs.
00026 msr PASSED: Test 1, MSR FEATURE_CONTROL (0x3a) (mask:ff07) was consistent
00027 msr across 2 CPUs.
00028 msr PASSED: Test 1, MSR BIOS_SIGN_ID (0x8b) (mask:ffffffff00000000) was
00029 msr consistent across 2 CPUs.
00030 msr PASSED: Test 1, MSR MTRRCAP (0xfe) (mask:fff) was consistent across 2
00031 msr CPUs.
00032 msr PASSED: Test 1, MSR SYSENTER_CS (0x174) (mask:ffff) was consistent
00033 msr across 2 CPUs.
00034 msr PASSED: Test 1, MSR SYSENTER_ESP (0x175) (mask:ffffffffffffffff) was
00035 msr consistent across 2 CPUs.
00036 msr PASSED: Test 1, MSR SYSENTER_EIP (0x176) (mask:ffffffffffffffff) was
00037 msr consistent across 2 CPUs.
00038 msr PASSED: Test 1, MSR MCG_CAP (0x179) (mask:1ff0fff) was consistent
00039 msr across 2 CPUs.
00040 msr PASSED: Test 1, MSR MCG_STATUS (0x17a) (mask:ffffffffffffffff) was
00041 msr consistent across 2 CPUs.
00042 msr FAILED [MEDIUM] MSRCPUsInconsistent: Test 1, MSR CLOCK_MODULATION
00043 msr (0x19a) has 1 inconsistent values across 2 CPUs for (shift: 0 mask:
00044 msr 0x1f).
00045 msr MSR CPU 0 -> 0x12 vs CPU 1 -> 0x0
00046 msr PASSED: Test 1, MSR THERM_INTERRUPT (0x19b) (mask:180801f) was
00047 msr consistent across 2 CPUs.
00048 msr PASSED: Test 1, MSR MISC_ENABLE (0x1a0) (mask:400c51889) was
00049 msr consistent across 2 CPUs.
00050 msr PASSED: Test 1, MSR PLATFORM_DCA_CAP (0x1f8) (mask:ffffffffffffffff)
00051 msr was consistent across 2 CPUs.
00052 msr PASSED: Test 1, MSR CPU_DCA_CAP (0x1f9) (mask:ffffffffffffffff) was
00053 msr consistent across 2 CPUs.
00054 msr PASSED: Test 1, MSR DCA_O_CAP (0x1fa) (mask:501e7ff) was consistent
00055 msr across 2 CPUs.
00056 msr PASSED: Test 1, MSR MTRR_PHYSBASE0 (0x200) (mask:ffffffffffffffff)
00057 msr was consistent across 2 CPUs.
00058 msr PASSED: Test 1, MSR MTRR_PHYSMASK0 (0x201) (mask:ffffffffffffffff)
00059 msr was consistent across 2 CPUs.
00060 msr PASSED: Test 1, MSR MTRR_PHYSBASE1 (0x202) (mask:ffffffffffffffff)
00061 msr was consistent across 2 CPUs.
00062 msr PASSED: Test 1, MSR MTRR_PHYSMASK1 (0x203) (mask:ffffffffffffffff)
00063 msr was consistent across 2 CPUs.
00064 msr PASSED: Test 1, MSR MTRR_PHYSBASE2 (0x204) (mask:ffffffffffffffff)
00065 msr was consistent across 2 CPUs.
00066 msr PASSED: Test 1, MSR MTRR_PHYSMASK2 (0x205) (mask:ffffffffffffffff)
00067 msr was consistent across 2 CPUs.
00068 msr PASSED: Test 1, MSR MTRR_PHYSBASE3 (0x206) (mask:ffffffffffffffff)
00069 msr was consistent across 2 CPUs.
00070 msr PASSED: Test 1, MSR MTRR_PHYSMASK3 (0x207) (mask:ffffffffffffffff)
00071 msr was consistent across 2 CPUs.
00072 msr PASSED: Test 1, MSR MTRR_PHYSBASE4 (0x208) (mask:ffffffffffffffff)
00073 msr was consistent across 2 CPUs.
00074 msr PASSED: Test 1, MSR MTRR_PHYSMASK4 (0x209) (mask:ffffffffffffffff)
00075 msr was consistent across 2 CPUs.
00076 msr PASSED: Test 1, MSR MTRR_PHYSBASE5 (0x20a) (mask:ffffffffffffffff)
00077 msr was consistent across 2 CPUs.
00078 msr PASSED: Test 1, MSR MTRR_PHYSMASK5 (0x20b) (mask:ffffffffffffffff)
00079 msr was consistent across 2 CPUs.
00080 msr PASSED: Test 1, MSR MTRR_PHYSBASE6 (0x20c) (mask:ffffffffffffffff)
00081 msr was consistent across 2 CPUs.
00082 msr PASSED: Test 1, MSR MTRR_PHYSMASK6 (0x20d) (mask:ffffffffffffffff)
00083 msr was consistent across 2 CPUs.
00084 msr PASSED: Test 1, MSR MTRR_PHYSBASE7 (0x20e) (mask:ffffffffffffffff)
00085 msr was consistent across 2 CPUs.
00086 msr PASSED: Test 1, MSR MTRR_PHYSMASK7 (0x20f) (mask:ffffffffffffffff)
00087 msr was consistent across 2 CPUs.
00088 msr PASSED: Test 1, MSR MTRR_FIX64K_000 (0x250) (mask:ffffffffffffffff)
00089 msr was consistent across 2 CPUs.
00090 msr PASSED: Test 1, MSR MTRR_FIX16K_800 (0x258) (mask:ffffffffffffffff)
00091 msr was consistent across 2 CPUs.
00092 msr PASSED: Test 1, MSR MTRR_FIX16K_a00 (0x259) (mask:ffffffffffffffff)
00093 msr was consistent across 2 CPUs.
00094 msr PASSED: Test 1, MSR MTRR_FIX4K_C000 (0x268) (mask:ffffffffffffffff)
00095 msr was consistent across 2 CPUs.
00096 msr PASSED: Test 1, MSR MTRR_FIX4K_C800 (0x269) (mask:ffffffffffffffff)
00097 msr was consistent across 2 CPUs.
00098 msr PASSED: Test 1, MSR MTRR_FIX4K_D000 (0x26a) (mask:ffffffffffffffff)
00099 msr was consistent across 2 CPUs.
00100 msr PASSED: Test 1, MSR MTRR_FIX4K_D800 (0x26b) (mask:ffffffffffffffff)
00101 msr was consistent across 2 CPUs.
00102 msr PASSED: Test 1, MSR MTRR_FIX4K_E000 (0x26c) (mask:ffffffffffffffff)
00103 msr was consistent across 2 CPUs.
00104 msr PASSED: Test 1, MSR MTRR_FIX4K_E800 (0x26d) (mask:ffffffffffffffff)
00105 msr was consistent across 2 CPUs.
00106 msr PASSED: Test 1, MSR MTRR_FIX4K_F000 (0x26e) (mask:ffffffffffffffff)
00107 msr was consistent across 2 CPUs.
00108 msr PASSED: Test 1, MSR MTRR_FIX4K_F800 (0x26f) (mask:ffffffffffffffff)
00109 msr was consistent across 2 CPUs.
00110 msr PASSED: Test 1, MSR PAT (0x277) (mask:707070707070703) was consistent
00111 msr across 2 CPUs.
00112 msr PASSED: Test 1, MSR MTRR_DEF_TYPE (0x2ff) (mask:c0f) was consistent
00113 msr across 2 CPUs.
00114 msr PASSED: Test 1, MSR PEBS_ENABLE (0x3f1) (mask:1) was consistent
00115 msr across 2 CPUs.
00116 msr PASSED: Test 1, MSR EFER (0xc0000080) (mask:d01) was consistent
00117 msr across 2 CPUs.
00118 msr PASSED: Test 1, MSR STAR (0xc0000081) (mask:ffffffffffffffff) was
00119 msr consistent across 2 CPUs.
00120 msr PASSED: Test 1, MSR LSTAR (0xc0000082) (mask:ffffffffffffffff) was
00121 msr consistent across 2 CPUs.
00122 msr PASSED: Test 1, MSR FMASK (0xc0000084) (mask:ffffffffffffffff) was
00123 msr consistent across 2 CPUs.
00124 msr PASSED: Test 1, MSR KERNEL_GS_BASE (0xc0000102) (mask
00125 msr :ffffffffffffffff) was consistent across 2 CPUs.
00126 msr
00127 msr Test 2 of 5: Check CPU specific model MSRs.
00128 msr No model specific tests for model 0xf.
00129 msr
00130 msr Test 3 of 5: Check all P State Ratios.
00131 msr PASSED: Test 3, MSR Minimum P-State (0xce) (mask:ff) was consistent
00132 msr across 2 CPUs.
00133 msr PASSED: Test 3, MSR Maximum P-State (0xce) (mask:ff) was consistent
00134 msr across 2 CPUs.
00135 msr
00136 msr Test 4 of 5: Check C1 and C3 autodemotion.
00137 msr PASSED: Test 4, MSR C1 and C3 Autodemotion (0xe2) (mask:3) was
00138 msr consistent across 2 CPUs.
00139 msr C1 and C3 Autodemotion disabled.
00140 msr
00141 msr Test 5 of 5: Check SMRR MSR registers.
00142 msr SMRR not supported by this CPU.
00143 msr
00144 msr ====================================================================
00145 msr 56 passed, 1 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.
00146 msr ====================================================================		 MSR register tests.
---------------------------------------------------------------------------------------------------
Test 1 of 5: Check CPU generic MSRs.
PASSED: Test 1, MSR P5_MC_TYPE (0x1) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MONITOR_FILTER_SIZE (0x6) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR PLATFORM_ID (0x17) (mask:1c000000000000) was consistent across 4 CPUs.
PASSED: Test 1, MSR EBL_CR_POWERON (0x2a) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR APIC_BASE (0x1b) (mask:fffffffffffffeff) was consistent across 4 CPUs.
PASSED: Test 1, MSR FEATURE_CONTROL (0x3a) (mask:ff07) was consistent across 4 CPUs.
PASSED: Test 1, MSR BIOS_SIGN_ID (0x8b) (mask:ffffffff00000000) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRRCAP (0xfe) (mask:fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR SYSENTER_CS (0x174) (mask:ffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR SYSENTER_ESP (0x175) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR SYSENTER_EIP (0x176) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MCG_CAP (0x179) (mask:1ff0fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MCG_STATUS (0x17a) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR CLOCK_MODULATION (0x19a) (mask:1f) was consistent across 4 CPUs.
PASSED: Test 1, MSR THERM_INTERRUPT (0x19b) (mask:180801f) was consistent across 4 CPUs.
PASSED: Test 1, MSR MISC_ENABLE (0x1a0) (mask:400c51889) was consistent across 4 CPUs.
PASSED: Test 1, MSR PACKAGE_THERM_INTERRUPT (0x1b2) (mask:1ffff17) was consistent across 4 CPUs.
PASSED: Test 1, MSR SMRR_PHYSBASE (0x1f2) (mask:fffff0ff) was consistent across 4 CPUs.
PASSED: Test 1, MSR SMRR_PHYSMASK (0x1f3) (mask:fffff800) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE0 (0x200) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK0 (0x201) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE1 (0x202) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK1 (0x203) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE2 (0x204) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK2 (0x205) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE3 (0x206) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK3 (0x207) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE4 (0x208) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK4 (0x209) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE5 (0x20a) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK5 (0x20b) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE6 (0x20c) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK6 (0x20d) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE7 (0x20e) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK7 (0x20f) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE8 (0x210) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK8 (0x211) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE9 (0x212) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK9 (0x213) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX64K_000 (0x250) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX16K_800 (0x258) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX16K_a00 (0x259) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_C000 (0x268) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_C800 (0x269) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_D000 (0x26a) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_D800 (0x26b) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_E000 (0x26c) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_E800 (0x26d) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_F000 (0x26e) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_F800 (0x26f) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR PAT (0x277) (mask:707070707070703) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC0_CTL2 (0x280) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC1_CTL2 (0x281) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC2_CTL2 (0x282) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC3_CTL2 (0x283) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC4_CTL2 (0x284) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC5_CTL2 (0x285) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC6_CTL2 (0x286) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_DEF_TYPE (0x2ff) (mask:c0f) was consistent across 4 CPUs.
PASSED: Test 1, MSR PEBS_ENABLE (0x3f1) (mask:1) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_BASIC (0x480) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_PINPASED_CTLS (0x481) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_PROCBASED_CTLS (0x482) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR VMX_EXIT_CTLS (0x483) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_ENTRY_CTLS (0x484) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_MISC (0x485) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_CR0_FIXED0 (0x486) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_CR0_FIXED1 (0x487) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_CR4_FIXED0 (0x488) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_CR4_FIXED1 (0x489) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_VMX_VMCS_ENUM (0x48a) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_PROCBASED_CTLS2 (0x48b) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR VMX_EPT_VPID_CAP (0x48c) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_TRUE_PINBASED_CTLS (0x48d) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR VMX_TRUE_PROCBASED_CTLS (0x48e) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR VMX_TRUE_EXIT_CTLS (0x48f) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR VMX_TRUE_ENTRY_CTLS (0x490) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR EFER (0xc0000080) (mask:d01) was consistent across 4 CPUs.
PASSED: Test 1, MSR STAR (0xc0000081) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR LSTAR (0xc0000082) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR FMASK (0xc0000084) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR KERNEL_GS_BASE (0xc0000102) (mask:ffffffffffffffff) was consistent across 4
CPUs.

Test 2 of 5: Check CPU specific model MSRs.
No model specific tests for model 0x3a.

Test 3 of 5: Check all P State Ratios.
PASSED: Test 3, MSR Minimum P-State (0xce) (mask:ff) was consistent across 4 CPUs.
PASSED: Test 3, MSR Maximum P-State (0xce) (mask:ff) was consistent across 4 CPUs.

Test 4 of 5: Check C1 and C3 autodemotion.
PASSED: Test 4, MSR C1 and C3 Autodemotion (0xe2) (mask:3) was consistent across 4 CPUs.
C1 and C3 Autodemotion enabled.

Test 5 of 5: Check SMRR MSR registers.
PASSED: Test 5, MSR SMRR_PHYSBASE (0x1f2) (mask:fffff) was consistent across 4 CPUs.
PASSED: Test 5, MSR SMRR_TYPE (0x1f2) (mask:7) was consistent across 4 CPUs.
PASSED: Test 5, MSR SMRR_PHYSMASK (0x1f3) (mask:fffff) was consistent across 4 CPUs.
PASSED: Test 5, MSR SMRR_VALID (0x1f3) (mask:1) was consistent across 4 CPUs.

===================================================================================================
89 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.
===================================================================================================

Firmware Test Suite - msr test

Intel and AMD processors provide special control registers known as Model Specific Registers (MSRs) allowing software to set and define specific features. The msr test will sanity check a range of MSRs to ensure consistency across CPUs and ensure sane values are configured by the firmware.

Five specific tests are performed:

  • Check CPU generic MSRs (ones common to most processors).
  • Check CPU specific model MSRs.
  • Check all P State Ratios.
  • Check C1 and C3 autodemotion.
  • Check SMRR MSR registers.

Typical output from this test is as follows: 

MSR register tests.
---------------------------------------------------------------------------------------------------
Test 1 of 5: Check CPU generic MSRs.
PASSED: Test 1, MSR P5_MC_TYPE (0x1) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MONITOR_FILTER_SIZE (0x6) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR PLATFORM_ID (0x17) (mask:1c000000000000) was consistent across 4 CPUs.
PASSED: Test 1, MSR EBL_CR_POWERON (0x2a) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR APIC_BASE (0x1b) (mask:fffffffffffffeff) was consistent across 4 CPUs.
PASSED: Test 1, MSR FEATURE_CONTROL (0x3a) (mask:ff07) was consistent across 4 CPUs.
PASSED: Test 1, MSR BIOS_SIGN_ID (0x8b) (mask:ffffffff00000000) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRRCAP (0xfe) (mask:fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR SYSENTER_CS (0x174) (mask:ffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR SYSENTER_ESP (0x175) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR SYSENTER_EIP (0x176) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MCG_CAP (0x179) (mask:1ff0fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MCG_STATUS (0x17a) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR CLOCK_MODULATION (0x19a) (mask:1f) was consistent across 4 CPUs.
PASSED: Test 1, MSR THERM_INTERRUPT (0x19b) (mask:180801f) was consistent across 4 CPUs.
PASSED: Test 1, MSR MISC_ENABLE (0x1a0) (mask:400c51889) was consistent across 4 CPUs.
PASSED: Test 1, MSR PACKAGE_THERM_INTERRUPT (0x1b2) (mask:1ffff17) was consistent across 4 CPUs.
PASSED: Test 1, MSR SMRR_PHYSBASE (0x1f2) (mask:fffff0ff) was consistent across 4 CPUs.
PASSED: Test 1, MSR SMRR_PHYSMASK (0x1f3) (mask:fffff800) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE0 (0x200) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK0 (0x201) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE1 (0x202) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK1 (0x203) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE2 (0x204) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK2 (0x205) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE3 (0x206) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK3 (0x207) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE4 (0x208) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK4 (0x209) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE5 (0x20a) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK5 (0x20b) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE6 (0x20c) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK6 (0x20d) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE7 (0x20e) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK7 (0x20f) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE8 (0x210) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK8 (0x211) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSBASE9 (0x212) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_PHYSMASK9 (0x213) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX64K_000 (0x250) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX16K_800 (0x258) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX16K_a00 (0x259) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_C000 (0x268) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_C800 (0x269) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_D000 (0x26a) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_D800 (0x26b) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_E000 (0x26c) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_E800 (0x26d) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_F000 (0x26e) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_FIX4K_F800 (0x26f) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR PAT (0x277) (mask:707070707070703) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC0_CTL2 (0x280) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC1_CTL2 (0x281) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC2_CTL2 (0x282) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC3_CTL2 (0x283) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC4_CTL2 (0x284) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC5_CTL2 (0x285) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MC6_CTL2 (0x286) (mask:40007fff) was consistent across 4 CPUs.
PASSED: Test 1, MSR MTRR_DEF_TYPE (0x2ff) (mask:c0f) was consistent across 4 CPUs.
PASSED: Test 1, MSR PEBS_ENABLE (0x3f1) (mask:1) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_BASIC (0x480) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_PINPASED_CTLS (0x481) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_PROCBASED_CTLS (0x482) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR VMX_EXIT_CTLS (0x483) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_ENTRY_CTLS (0x484) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_MISC (0x485) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_CR0_FIXED0 (0x486) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_CR0_FIXED1 (0x487) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_CR4_FIXED0 (0x488) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_CR4_FIXED1 (0x489) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_VMX_VMCS_ENUM (0x48a) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_PROCBASED_CTLS2 (0x48b) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR VMX_EPT_VPID_CAP (0x48c) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR VMX_TRUE_PINBASED_CTLS (0x48d) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR VMX_TRUE_PROCBASED_CTLS (0x48e) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR VMX_TRUE_EXIT_CTLS (0x48f) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR VMX_TRUE_ENTRY_CTLS (0x490) (mask:ffffffffffffffff) was consistent across 4
CPUs.
PASSED: Test 1, MSR EFER (0xc0000080) (mask:d01) was consistent across 4 CPUs.
PASSED: Test 1, MSR STAR (0xc0000081) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR LSTAR (0xc0000082) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR FMASK (0xc0000084) (mask:ffffffffffffffff) was consistent across 4 CPUs.
PASSED: Test 1, MSR KERNEL_GS_BASE (0xc0000102) (mask:ffffffffffffffff) was consistent across 4
CPUs.

Test 2 of 5: Check CPU specific model MSRs.
No model specific tests for model 0x3a.

Test 3 of 5: Check all P State Ratios.
PASSED: Test 3, MSR Minimum P-State (0xce) (mask:ff) was consistent across 4 CPUs.
PASSED: Test 3, MSR Maximum P-State (0xce) (mask:ff) was consistent across 4 CPUs.

Test 4 of 5: Check C1 and C3 autodemotion.
PASSED: Test 4, MSR C1 and C3 Autodemotion (0xe2) (mask:3) was consistent across 4 CPUs.
C1 and C3 Autodemotion enabled.

Test 5 of 5: Check SMRR MSR registers.
PASSED: Test 5, MSR SMRR_PHYSBASE (0x1f2) (mask:fffff) was consistent across 4 CPUs.
PASSED: Test 5, MSR SMRR_TYPE (0x1f2) (mask:7) was consistent across 4 CPUs.
PASSED: Test 5, MSR SMRR_PHYSMASK (0x1f3) (mask:fffff) was consistent across 4 CPUs.
PASSED: Test 5, MSR SMRR_VALID (0x1f3) (mask:1) was consistent across 4 CPUs.

===================================================================================================
89 passed, 0 failed, 0 warnings, 0 aborted, 0 skipped, 0 info only.
===================================================================================================

Note that the "mask:0x" shows the particular bits that were examined on each MSR.

Examples:

sudo fwts msr -

..runs the msr test on your machine and dumps the output to stdout. 

sudo fwts msr

..runs the msr test on your machine and appends the output to the default logfile results.log

Explanation of test results

Certain test results may require a little more explanation. This section will try and give some context to specific test failures.

Error ID

Explanation

MSRCPUsInconsistent

A specific MSR is not consistently set across all CPUs.

MSRSMRR_PHYSBASE8MBBoundary

SMRR_PHYSBASE is NOT on an 8MB boundary.

MSRSMRR_TYPE

SMRR_TYPE was expected to be 0x06 (Write-back).

MSRSMRRRegion

SMRR region needs to be at least 8MB in size.

MSRSMRRValidBit

SMRR valid bit is zero and should be one.

FirmwareTestSuite/Reference/msr (last edited 2016-01-11 07:24:41 by anthonywong)