Important documents to Ubuntu on POWER

Comprehensive PMU Event Reference

The POWER7 processor has a built in performance monitoring unit (PMU) for each hardware thread, which provides instrumentation to aid in performance monitoring, workload characterization, system characterization and code analysis. There are 6 thread-level Performance Monitor Counters (PMC) in a PMU. PMC1 – PMC4 are programmable, PMC5 counts non idle completed instructions and PMC6 counts non idle cycles. The thread level and core level instrumentation have access to a rich set of performance events (close to 550) that cover essential statistics such as miss rates, unit utilization, thread balance, hazard conditions, translation related misses, stall analysis, instruction mix, L1 I cache and D cache reload source, effective cache counts and memory latency counts. This document covers all of the performance monitoring events supported by…

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ppc64el/References (last edited 2016-06-03 14:09:20 by chris-gondolin)